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| k50p100m100sf2v2 k50 sub-family supports the following: MK50DX256CLL10, mk50dn512cll10 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 85c ? performance C up to 100 mhz arm cortex-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 512 kb program flash memory on non- flexmemory devices C up to 256 kb program flash memory on flexmemory devices C up to 256 kb flexnvm on flexmemory devices C 4 kb flexram on flexmemory devices C up to 128 kb ram C serial programming interface (ezport) C flexbus external bus interface ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C multiple low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 16-channel dma controller, supporting up to 63 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C 128-bit unique identification (id) number per chip ? analog modules C two 16-bit sar adcs C programmable gain amplifier (pga) (up to x64) integrated into each adc C two 12-bit dacs C two operational amplifiers C two transimpedance amplifiers C three analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C eight-channel motor control/general purpose/pwm timer C two 2-channel quadrature decoder/general purpose timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock ? communication interfaces C usb full-/low-speed on-the-go controller with on- chip transceiver C three spi modules C two i2c modules C five uart modules C secure digital host controller (sdhc) C i2s module freescale semiconductor document number: k50p100m100sf2v2 data sheet: advance information rev. 1, 6/2012 this document contains information on a new product. specifications and information herein are subject to change without notice. ? 2012 freescale semiconductor, inc. preliminary general business information
table of contents 1 ordering parts ........................................................................... 4 1.1 determining valid orderable parts...................................... 4 2 part identification ...................................................................... 4 2.1 description......................................................................... 4 2.2 format ............................................................................... 4 2.3 fields ................................................................................. 4 2.4 example ............................................................................ 5 3 terminology and guidelines ...................................................... 5 3.1 definition: operating requirement...................................... 5 3.2 definition: operating behavior ........................................... 6 3.3 definition: attribute ............................................................ 6 3.4 definition: rating ............................................................... 7 3.5 result of exceeding a rating .............................................. 7 3.6 relationship between ratings and operating requirements...................................................................... 7 3.7 guidelines for ratings and operating requirements............ 8 3.8 definition: typical value..................................................... 8 3.9 typical value conditions .................................................... 9 4 ratings ...................................................................................... 10 4.1 thermal handling ratings ................................................... 10 4.2 moisture handling ratings .................................................. 10 4.3 esd handling ratings ......................................................... 10 4.4 voltage and current operating ratings ............................... 10 5 general ..................................................................................... 11 5.1 ac electrical characteristics .............................................. 11 5.2 nonswitching electrical specifications ............................... 11 5.2.1 voltage and current operating requirements ......... 12 5.2.2 lvd and por operating requirements ................. 13 5.2.3 voltage and current operating behaviors .............. 13 5.2.4 power mode transition operating behaviors .......... 14 5.2.5 power consumption operating behaviors .............. 15 5.2.6 emc radiated emissions operating behaviors....... 18 5.2.7 designing with radiated emissions in mind ........... 19 5.2.8 capacitance attributes .......................................... 19 5.3 switching specifications..................................................... 19 5.3.1 device clock specifications ................................... 19 5.3.2 general switching specifications ........................... 20 5.4 thermal specifications ....................................................... 21 5.4.1 thermal operating requirements ........................... 21 5.4.2 thermal attributes ................................................. 21 6 peripheral operating requirements and behaviors .................... 22 6.1 core modules .................................................................... 22 6.1.1 debug trace timing specifications ......................... 22 6.1.2 jtag electricals .................................................... 23 6.2 system modules ................................................................ 26 6.3 clock modules ................................................................... 26 6.3.1 mcg specifications ............................................... 26 6.3.2 oscillator electrical specifications ......................... 28 6.3.3 32 khz oscillator electrical characteristics........... 31 6.4 memories and memory interfaces ..................................... 31 6.4.1 flash electrical specifications................................ 31 6.4.2 ezport switching specifications ............................ 36 6.4.3 flexbus switching specifications .......................... 37 6.5 security and integrity modules .......................................... 40 6.6 analog ............................................................................... 40 6.6.1 adc electrical specifications ................................. 40 6.6.2 cmp and 6-bit dac electrical specifications ......... 48 6.6.3 12-bit dac electrical characteristics ..................... 51 6.6.4 op-amp electrical specifications ........................... 54 6.6.5 transimpedance amplifier electrical specifications full range .................................... 55 6.6.6 transimpedance amplifier electrical specifications limited range .............................. 56 6.6.7 voltage reference electrical specifications ............ 57 6.7 timers................................................................................ 58 6.8 communication interfaces ................................................. 58 6.8.1 usb electrical specifications ................................. 58 6.8.2 usb dcd electrical specifications ........................ 59 6.8.3 usb vreg electrical specifications ...................... 59 6.8.4 dspi switching specifications (limited voltage range) .................................................................... 60 6.8.5 dspi switching specifications (full voltage range). 61 6.8.6 i2c switching specifications .................................. 63 6.8.7 uart switching specifications .............................. 63 6.8.8 sdhc specifications ............................................. 63 6.8.9 i2s/sai switching specifications .......................... 64 6.9 human-machine interfaces (hmi)...................................... 71 6.9.1 tsi electrical specifications ................................... 71 7 dimensions ............................................................................... 72 7.1 obtaining package dimensions ......................................... 72 k50 sub-family data sheet, rev. 1, 6/2012. 2 preliminary freescale semiconductor, inc. general business information 8 pinout ........................................................................................ 72 8.1 k50 signal multiplexing and pin assignments .................. 72 8.2 k50 pinouts ....................................................................... 77 k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 3 general business information 1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: pk50 and mk50. 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status m = fully qualified, general market flow p = prequalification k## kinetis family k50 a key attribute d = cortex-m4 w/ dsp f = cortex-m4 w/ dsp and fpu m flash memory type n = program flash only x = program flash and flexmemory table continues on the next page... rdering parts 50 sub-family data sheet, rev. 1, /2012. preliminary freescale semiconductor, inc. general business information field description values fff program flash memory size 32 = 32 kb 64 = 64 kb 128 = 128 kb 256 = 256 kb 512 = 512 kb 1m0 = 1 mb r silicon revision z = initial (blank) = main a = revision after main t temperature range (?c) v = 40 to 105 c = 40 to 85 pp package identifier fm = 32 qfn (5 mm x 5 mm) ft = 48 qfn (7 mm x 7 mm) lf = 48 lqfp (7 mm x 7 mm) lh = 64 lqfp (10 mm x 10 mm) mp = 64 mapbga (5 mm x 5 mm) lk = 80 lqfp (12 mm x 12 mm) mb = 81 mapbga (8 mm x 8 mm) ll = 100 lqfp (14 mm x 14 mm) ml = 104 mapbga (8 mm x 8 mm) mc = 121 mapbga (8 mm x 8 mm) lq = 144 lqfp (20 mm x 20 mm) md = 144 mapbga (13 mm x 13 mm) mj = 256 mapbga (17 mm x 17 mm) cc maximum cpu frequency (mhz) 5 = 50 mhz 7 = 72 mhz 10 = 100 mhz 12 = 120 mhz 15 = 150 mhz n packaging type r = tape and reel (blank) = trays 2.4 example this is an example part number: mk50dn512zvmd10 3 terminology and guidelines 3.1 definition: operating requirement an operating requirement is a speciied value or range o values or a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useul lie o the chip erminology and guidelines ubamily ata heet ev reescale emiconductor nc reliminary eneral usiness normation 3.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 3.2 definition: operating behavior an operating behavior is a speciied value or range o values or a technical characteristic that are guaranteed during operation i you meet the operating requirements and any other speciied conditions ample his is an eample o an operating behavior hich is guaranteed i you meet the accompanying operating requirements ymbol escription in a nit igital o ea pullup pulldon current einition ttribute n attribute is a speciied value or range o values or a technical characteristic that are guaranteed regardless o hether you meet the operating requirements ample his is an eample o an attribute ymbol escription in a nit nput capacitance digital pins p erminology and guidelines ubamily ata heet ev reliminary reescale emiconductor nc eneral usiness normation 3.4 definition: rating a rating is a minimum or maimum value o a technical characteristic that i eceeded may cause permanent chip ailure operating ratings apply during operation o the chip handling ratings apply hen the chip is not poered ample his is an eample o an operating rating ymbol escription in a nit core supply voltage esult o eceeding a rating easured characteristic operating rating ailures in time ppm he lielihood o permanent chip ailure increases rapidly as soon as a characteristic begins to eceed one o its operating ratings erminology and guidelines ubamily ata heet ev reescale emiconductor nc reliminary eneral usiness normation 3.6 relationship between ratings and operating requirements typical value is a speciied value or a technical characteristic that ies ithin the range o values speciied by the operating behavior iven the typical manuacturing process is representative o that characteristic during operation hen you meet the typicalvalue conditions or other speciied conditions ypical values are provided as design guidelines and are neither tested nor guaranteed erminology and guidelines ubamily ata heet ev reliminary reescale emiconductor nc eneral usiness normation 3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 ?c 105 ?c 25 ?c 40 ?c v dd (v) i (?a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 ?c v dd 3.3 v supply voltage 3.3 v terminology and guidelines k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 9 general business information 4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature 55 150 ?c 1 t sdr solder temperature, lead-free 260 ?c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . .2 moisture handling ratings symbol description min. max. nit notes msl moisture sensitivity level 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . . esd handling ratings symbol description min. max. nit notes hbm electrostatic discharge voltage, human body model -2000 2000 1 cdm electrostatic discharge voltage, charged-device model -500 500 2 i lat latch-up current at ambient temperature of 105c -100 100 ma 1. determined according to jedec standard jesd22-a11, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . . oltage and current operating ratings symbol description min. max. nit dd digital supply voltage 0. . table continues on the next page... ratings 50 sub-family data sheet, rev. 1, /2012. 10 preliminary freescale semiconductor, inc. general business information symbol description min. max. unit i dd digital supply current 185 ma v dio digital input voltage (except reset, extal, and xtal) 0.3 5.5 v v aio analog 1 , reset, extal, and xtal input voltage 0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all port pins) 25 25 ma v dda analog supply voltage v dd 0.3 v dd + 0.3 v v usb_dp usb_dp input voltage 0.3 3.63 v v usb_dm usb_dm input voltage 0.3 3.63 v vregin usb regulator input 0.3 6.0 v v bat rtc battery supply voltage 0.3 3.8 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 1. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) general k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 11 general business information 5.2 nonswitching electrical specifications 5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd v dda v dd -to-v dda differential voltage 0.1 0.1 v v ss v ssa v ss -to-v ssa differential voltage 0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icdio digital pin negative dc injection current single pin v in < v ss -0.3v -5 ma 1 i icaio analog 2 , extal, and xtal pin dc injection current single pin v in < v ss -0.3v (negative current injection) v in > v dd +0.3v (positive current injection) -5 +5 ma 3 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins negative current injection positive current injection -25 +25 ma v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all 5 v tolerant digital i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v dio_min (=v ss -0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i ic |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is greater than v aio_min (=v ss -0.3v) and v in is less than v aio_max (=v dd +0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if these limits cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i ic |. the positive injection current limiting resistor is calcualted as r=(v in -v aio_max )/|i ic |. select the larger of these two calculated resistances. general k50 sub-family data sheet, rev. 1, 6/2012. 12 preliminary freescale semiconductor, inc. general business information 5.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 ?s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v general k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 13 general business information 5.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength 2.7 v ? v dd ? 3.6 v, i oh = -9ma 1.71 v ? v dd ? 2.7 v, i oh = -3ma v dd 0.5 v dd 0.5 v v output high voltage low drive strength 2.7 v ? v dd ? 3.6 v, i oh = -2ma 1.71 v ? v dd ? 2.7 v, i oh = -0.6ma v dd 0.5 v dd 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage high drive strength 2.7 v ? v dd ? 3.6 v, i ol = 9ma 1.71 v ? v dd ? 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength 2.7 v ? v dd ? 3.6 v, i ol = 2ma 1.71 v ? v dd ? 2.7 v, i ol = 0.6ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range except tri0_dm, tri0_dp, tri1_dm, tri1_dp 1 ?a 1 i in input leakage current (per pin) at 25?c except tri0_dm, tri0_dp, tri1_dm, tri1_dp 0.025 ?a 1 i ilkg_a input leakage current (per pin) for tri0_dm, tri0_dp, tri1_dm, tri1_dp 5 na 1 i oz hi-z (off-state) leakage current (per pin) 1 ?a r pu internal pullup resistors 20 50 k? 2 r pd internal pulldown resistors 20 50 k? 3 1. measured at vdd=3.6v 2. measured at v dd supply voltage = v dd min and vinput = v ss 3. measured at v dd supply voltage = v dd min and vinput = v dd 5.2.4 power mode transition operating behaviors all specifications except t por , and vllsx ? flexbus clock = 50 mhz ? flash clock = 25 mhz table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 ?s 1 vlls1 table continues on the next page... general 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 15 general business information table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.71 ma 7 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.77 ma 8 i dd_stop stop mode current at 3.0 v @ 40 to 25?c @ 70?c @ 105?c 0.74 2.45 6.61 tbd tbd tbd ma ma ma i dd_vlps very-low-power stop mode current at 3.0 v @ 40 to 25?c @ 70?c @ 105?c 83 425 1280 tbd tbd tbd ?a ?a ?a i dd_lls low leakage stop mode current at 3.0 v @ 40 to 25?c @ 70?c @ 105?c 4.58 30.6 137 tbd tbd tbd ?a ?a ?a 9 i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v @ 40 to 25?c @ 70?c @ 105?c 3.0 18.6 84.9 tbd tbd tbd ?a ?a ?a 9 i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v @ 40 to 25?c @ 70?c @ 105?c 2.2 9.3 41.4 tbd tbd tbd ?a ?a ?a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v @ 40 to 25?c @ 70?c @ 105?c 2.1 7.6 33.5 tbd tbd tbd ?a ?a ?a i dd_vbat average current with rtc and 32khz disabled at 3.0 v @ 40 to 25?c @ 70?c @ 105?c 0.19 0.49 2.2 0.22 0.64 3.2 ?a ?a ?a table continues on the next page... general 50 sub-family data sheet, rev. 1, /2012. 1 preliminary freescale semiconductor, inc. general business information table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vbat average current when cpu is not accessing rtc registers @ 1.8v @ 40 to 25?c @ 70?c @ 105?c @ 3.0v @ 40 to 25?c @ 70?c @ 105?c 0.57 0.90 2.4 0.67 1.0 2.7 0.67 1.2 3.5 0.94 1.4 3.9 ?a ?a ?a ?a ?a ?a 10 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module?s specification for its supply current. 2. 100mhz core and system clock, 50mhz bus and flexbus clock, and 25mhz flash clock . mcg configured for fei mode. all peripheral clocks disabled. 3. 100mhz core and system clock, 50mhz bus and flexbus clock, and 25mhz flash clock. mcg configured for fei mode. all peripheral clocks enabled. 4. max values are measured with cpu executing dsp instructions. 5. 25mhz core and system clock, 25mhz bus clock, and 12.5mhz flexbus and flash clock. mcg configured for fei mode. 6. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 7. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 8. 4 mhz core, system, flexbus, and bus clock and 1mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 9. data reflects devices with 128 kb of ram. for devices with 64 kb of ram, power consumption is reduced by 2 ?a. 10. includes 32khz oscillator current and rtc operation. 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at greater than 50 mhz frequencies. ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfl general k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 17 general business information figure 2. run mode supply current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors for 144lqfp symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.1550 23 db?v 1 , 2 v re2 radiated emissions voltage, band 2 50150 27 db?v v re3 radiated emissions voltage, band 3 150500 28 db?v v re4 radiated emissions voltage, band 4 5001000 14 db?v v re_iec iec level 0.151000 k 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 1-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each freuency range. general 50 sub-family data sheet, rev. 1, /2012. 1 preliminary freescale semiconductor, inc. general business information 2. v dd = 3.3 v, t a = 25 ?c, f osc = 12 mhz (crystal), f sys = 96 mhz, f bus = 48mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 5.2. designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to http://www.freescale.com . 2. perform a keyword search for emc design. 5.2. capacitance attributes table . capacitance attributes symbol description min. max. nit c ina input capacitance: analog pins pf c ind input capacitance: digital pins pf 5. switching specifications 5..1 device clock specifications table . device clock specifications symbol description min. max. nit notes normal run mode f ss system and core clock 100 mhz f sssb system and core clock when full speed sb in operation 20 mhz f bs bus clock 50 mhz fbcl flexbus clock 50 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz lpr mode 1 f ss system and core clock mhz f bs bus clock mhz fbcl flexbus clock mhz f flash flash clock 1 mhz table continues on the next page... general 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 1 general business information table 9. device clock specifications (continued) symbol description min. max. unit notes f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz f lptmr_erclk lptmr external reference clock 16 mhz f flexcan_erclk flexcan external reference clock 8 mhz f i2s_mclk i2s master clock 12.5 mhz f i2s_bclk i2s bit clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, cmt, and i 2 c signals. table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) slew disabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v slew enabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v 12 6 36 24 ns ns ns ns 4 table continues on the next page... general 50 sub-family data sheet, rev. 1, /2012. 20 preliminary freescale semiconductor, inc. general business information table 10. general switching specifications (continued) symbol description min. max. unit notes port rise and fall time (low drive strength) slew disabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v slew enabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v 12 6 36 24 ns ns ns ns 5 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 75pf load 5. 15pf load 5.4 thermal specifications 5.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature 40 125 ?c t a ambient temperature 40 85 ?c 5.4.2 thermal attributes board type symbol description 100 lqfp unit notes single-layer (1s) r table continues on the next page... general 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 21 general business information board type symbol description 100 lqfp unit notes single-layer (1s) r integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/jedec standard jesd51-, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-, integrated circuit thermal test method environmental conditionsjunction-to-board . . determined according to method 1012.1 of mil-std , test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. . determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . peripheral operating reuirements and behaviors .1 core modules .1.1 debug trace timing specifications table 12. debug trace operating behaviors symbol description min. max. nit t cyc clock period freuency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time ns table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. 22 preliminary freescale semiconductor, inc. general business information table 12. debug trace operating behaviors (continued) symbol description min. max. unit t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns figure 3. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 4. trace data specifications 6.1.2 jtag electricals table 13. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width boundary scan jtag and cjtag serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 2 general business information table 13. jtag limited voltage range electricals (continued) symbol description min. max. unit j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 17 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 14. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation boundary scan jtag and cjtag serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width boundary scan jtag and cjtag serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 0 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 22.1 ns j12 tclk low to tdo high-z 22.1 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 24 preliminary freescale semiconductor, inc. general business information j2 j3 j3 j4 j4 tclk (input) figure 5. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 6. boundary scan (jtag) timing peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 25 general business information j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 7. test access port timing j14 j13 tclk trst figure 8. trst timing 6.2 system modules there are no specifications necessary for the devices system modules. 6.3 clock modules peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 26 preliminary freescale semiconductor, inc. general business information 6.3.1 mcg specifications table 15. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 ?c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 2 general business information table 15. mcg specifications (continued) symbol description min. typ. max. unit notes j cyc_fll fll period jitter f vco = 48 mhz f vco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 7 i pll pll operating current pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 7 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) f vco = 48 mhz f vco = 100 mhz 120 50 ps ps 8 j acc_pll pll accumulated jitter over 1s (rms) f vco = 48 mhz f vco = 100 mhz 1350 600 ps ps 8 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 9 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 16. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 500 200 300 950 1.2 1.5 na ?a ?a ?a ma ma 1 i ddosc supply current high gain mode (hgo=1) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 25 400 500 2.5 3 4 ?a ?a ?a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m? 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m? feedback resistor high-frequency, low-power mode (hgo=0) m? feedback resistor high-frequency, high-gain mode (hgo=1) 1 m? r s series resistor low-frequency, low-power mode (hgo=0) k? series resistor low-frequency, high-gain mode (hgo=1) 200 k? series resistor high-frequency, low-power mode (hgo=0) k? series resistor high-frequency, high-gain mode (hgo=1) 0 k? table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 2 general business information table 16. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 ?c 2. see crystal or resonator manufacturer?s recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 17. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 30 preliminary freescale semiconductor, inc. general business information 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.3.3 32 khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32 khz oscillator dc electrical specifications table 18. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m? c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 32khz oscillator frequency specifications table 19. 32khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 6.4 memories and memory interfaces 6.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 31 general business information 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 20. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 ?s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk256k erase block high-voltage time for 256 kb 104 904 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 21. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk256k read 1s block execution time 256 kb program/data flash 1.7 ms t rd1sec2k read 1s section execution time (flash sector) 60 ?s 1 t pgmchk program check execution time 45 ?s 1 t rdrsrc read resource execution time 30 ?s 1 t pgm4 program longword execution time 65 145 ?s t ersblk256k erase flash block execution time 256 kb program/data flash 122 985 ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t pgmsec512 t pgmsec1k t pgmsec2k program section execution time 512 b flash 1 kb flash 2 kb flash 2.4 4.7 9.3 ms ms ms t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 ?s 1 t pgmonce program once execution time 65 ?s t ersall erase all blocks execution time 250 2000 ms 2 t vfykey verify backdoor access key execution time 30 ?s 1 t swapx01 t swapx02 t swapx04 t swapx08 swap control execution time control code 0x01 control code 0x02 control code 0x04 control code 0x08 200 70 70 150 150 30 ?s ?s ?s ?s table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. 2 preliminary freescale semiconductor, inc. general business information table 21. flash command timing specifications (continued) symbol description min. typ. max. unit notes t pgmpart64k t pgmpart256k program partition for eeprom execution time 64 kb flexnvm 256 kb flexnvm 138 145 ms ms t setramff t setram32k t setram64k t setram256k set flexram function execution time: control code 0xff 32 kb eeprom backup 64 kb eeprom backup 256 kb eeprom backup 70 0.8 1.3 4.5 1.2 1.9 5.5 ?s ms ms ms byte-write to flexram for eeprom operation t eewr8bers byte-write to erased flexram location execution time 175 260 ?s 3 t eewr8b32k t eewr8b64k t eewr8b128k t eewr8b256k byte-write to flexram execution time: 32 kb eeprom backup 64 kb eeprom backup 128 kb eeprom backup 256 kb eeprom backup 385 475 650 1000 1800 2000 2400 3200 ?s ?s ?s ?s word-write to flexram for eeprom operation t eewr16bers word-write to erased flexram location execution time 175 260 ?s t eewr16b32k t eewr16b64k t eewr16b128k t eewr16b256k word-write to flexram execution time: 32 kb eeprom backup 64 kb eeprom backup 128 kb eeprom backup 256 kb eeprom backup 385 475 650 1000 1800 2000 2400 3200 ?s ?s ?s ?s longword-write to flexram for eeprom operation t eewr32bers longword-write to erased flexram location execution time 360 540 ?s t eewr32b32k t eewr32b64k t eewr32b128k t eewr32b256k longword-write to flexram execution time: 32 kb eeprom backup 64 kb eeprom backup 128 kb eeprom backup 256 kb eeprom backup 630 810 1200 1900 2050 2250 2675 3500 ?s ?s ?s ?s 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 33 general business information 6.4.1.3 flash high voltage current behaviors table 22. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 6.4.1.4 reliability specifications table 23. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years t nvmretd1k data retention after up to 1 k cycles 20 100 years n nvmcycd cycling endurance 10 k 50 k cycles 2 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years t nvmretee10 data retention up to 10% of write endurance 20 100 years n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k n nvmwree32k write endurance eeprom backup to flexram ratio = 16 eeprom backup to flexram ratio = 128 eeprom backup to flexram ratio = 512 eeprom backup to flexram ratio = 4096 eeprom backup to flexram ratio = 32,768 35 k 315 k 1.27 m 10 m 80 m 175 k 1.6 m 6.4 m 50 m 400 m writes writes writes writes writes 3 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25?c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40?c ? t j ? 125?c. 3. write endurance represents the number of writes to each flexram location at -40?c ?tj ? 125?c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup per subsystem. minimum and typical values assume all byte-writes to flexram. 6.4.1.5 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 34 preliminary freescale semiconductor, inc. general business information the bytes not assigned to data flash via the flexnvm partition code are used by the flash memory module to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_subsystem = write_efficiency n eeprom 2 eeesplit eeesize eeesplit eeesize nvmcycd where ? writes_subsystem ? minimum number of writes to each flexram location for subsystem (each subsystem can have different endurance) ? eeprom ? allocated flexnvm for each eeprom subsystem based on depart; entered with the program partition command ? eeesplit ? flexram split factor for subsystem; entered with the program partition command ? eeesize ? allocated flexram based on depart; entered with the program partition command ? write_efficiency ? ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycd ? data flash cycling endurance (the following graph assumes 10,000 cycles) peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 35 general business information figure 9. eeprom backup writes to flexram 6.4.2 ezport switching specifications table 24. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 16 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 36 preliminary freescale semiconductor, inc. general business information ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 10. ezport timing diagram 6.4.3 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 25. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 20 ns fb2 address, data, and control output valid 11.5 ns 1 fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 8.5 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fbcs n , fbe, fbr/ w, fbtbst, fbtsi1:0, fbale, and fbts. peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary general business information 2. specification is valid for all fb_ad[31:0] and fb_ta. table 26. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 13.5 ns 1 fb3 address, data, and control output hold 0 ns 1 fb4 data and fb_ta input setup 13.7 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fbcs n , fbe, fbr/ w, fbtbst, fbtsi1:0, fbale, and fbts. 2. specification is valid for all fbad1:0 and fbta. peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. preliminary freescale semiconductor, inc. general business information address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb5 fb4 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 11. flexbus read timing diagram peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 39 general business information address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] figure 12. flexbus write timing diagram 6.5 security and integrity modules there are no specifications necessary for the devices security and integrity modules. 6.6 analog peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 40 preliminary freescale semiconductor, inc. general business information 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 27 and table 28 are achievable on the differential pins adcx_dp0, adcx_dm0, adcx_dp1, adcx_dm1, adcx_dp3, and adcx_dm3. the adcx_dp2 and adcx_dm2 adc inputs are connected to the pga outputs and are not direct device pins. accuracy specifications for these pins are defined in table 29 and table 30 . all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 27. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 1 general business information table 27. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate 16 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25?c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance should be kept as low as possible in order to achieve the best results. the results in this datasheet were derived from a system which has <8 ? analog source resistance. the r as / c as time constant should be kept to <1ns. 4. to use the maximum adc conversion clock frequency, the adhsc bit should be set and the adlpc bit should be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 r as v as c as z as v adin z adin r adin r adin r adin r adin c adin input pin input pin input pin input pin table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. 2 preliminary freescale semiconductor, inc. general business information table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes f adack adc asynchronous clock source adlpc=1, adhsc=0 adlpc=1, adhsc=1 adlpc=0, adhsc=0 adlpc=0, adhsc=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error 12 bit modes <12 bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity 12 bit modes <12 bit modes 0.7 0.2 -1.1 to +1.9 -0.3 to 0.5 lsb 4 5 inl integral non- linearity 12 bit modes <12 bit modes 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 e fs full-scale error 12 bit modes <12 bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 e q quantization error 16 bit modes ?13 bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16 bit differential mode avg=32 avg=4 16 bit single-ended mode avg=32 avg=4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16 bit differential mode avg=32 16 bit single-ended mode avg=32 94 -85 db db 7 sfdr spurious free dynamic range 16 bit differential mode avg=32 16 bit single-ended mode avg=32 82 78 95 90 db db 7 table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary general business information table 28. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes e il input leakage error i in r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) temp sensor slope 40?c to 105?c 1.715 mv/?c v temp25 temp sensor voltage 25?c 719 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25?c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit should be set, the hsc bit should be clear with 1mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock <16mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock <12mhz. 7. input data is 1 khz sine wave. adc conversion clock <12mhz. figure 14. typical enob vs. adc_clk for 16-bit differential mode peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 44 preliminary freescale semiconductor, inc. general business information figure 15. typical enob vs. adc_clk for 16-bit single-ended mode 6.6.1.3 16-bit adc with pga operating conditions table 29. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vref_ou t vref_ou t vref_ou t v 2 , 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differential input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k? in+ to in- 4 r as analog source resistance 100 ? 5 t s adc sampling time 1.25 s 6 table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 5 general business information table 29. 16-bit adc with pga operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate ? 13 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 18.484 450 ksps 7 16 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 37.037 250 ksps 8 1. typical values assume v dda = 3.0 v, temp = 25?c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vref_out) 3. pga reference is internally connected to the vref_out pin. if the user wishes to drive vref_out with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedance of the driven input is r pgad /2 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 7. adc clock = 18 mhz, adlsmp = 1, adlst = 00, adhsc = 1 8. adc clock = 12 mhz, adlsmp = 1, adlst = 01, adhsc = 1 6.6.1.4 16-bit adc with pga characteristics with chop enabled (adc_pga[pgachpb] =0) table 30. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current low power (adc_pga[pgalpb]=0) 420 644 ?a 2 i dc_pga input dc current a 3 gain =1, v refpga =1.2v, v cm =0.5v 1.54 ?a gain =64, v refpga =1.2v, v cm =0.1v 0.57 ?a table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. preliminary freescale semiconductor, inc. general business information table 30. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes g gain 4 pgag=0 pgag=1 pgag=2 pgag=3 pgag=4 pgag=5 pgag=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 1 2 4 8 16 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 r as < 100 table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary general business information table 30. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes thd total harmonic distortion gain=1 gain=64 85 49 100 95 db db 16-bit differential mode, average=32, f in =100hz sfdr spurious free dynamic range gain=1 gain=64 85 53 105 88 db db 16-bit differential mode, average=32, f in =100hz enob effective number of bits gain=1, average=4 gain=1, average=8 gain=64, average=4 gain=64, average=8 gain=1, average=32 gain=2, average=32 gain=4, average=32 gain=8, average=32 gain=16, average=32 gain=32, average=32 gain=64, average=32 11.6 8.0 7.2 6.3 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 13.6 9.6 9.6 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits bits bits 16-bit differential mode,f in =100hz sinad signal-to-noise plus distortion ratio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25?c, f adck =6mhz unless otherwise stated. 2. this current is a pga module adder, in addition to adc conversion currents. 3. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function of input common mode voltage (v cm ) and the pga gain. 4. gain = 2 pgag 5. after changing the pga gain setting, a minimum of 2 adc+pga conversions should be ignored. 6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. 6.6.2 cmp and 6-bit dac electrical specifications table 31. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 ?a i ddls supply current, low-speed mode (en=1, pmode=0) 20 ?a v ain analog input voltage v ss 0.3 v dd v table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. preliminary freescale semiconductor, inc. general business information table 31. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 cr0[hystctr] = 00 cr0[hystctr] = 01 cr0[hystctr] = 10 cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 ?s i dac6b 6-bit dac current adder (enabled) 7 ?a inl 6-bit dac integral non-linearity 0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity 0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 49 general business information 0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 16. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 50 preliminary freescale semiconductor, inc. general business information 0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 17. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 32. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature 40 105 ?c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be vdda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 51 general business information 6.6.3.2 12-bit dac operating behaviors table 33. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode tbd ?a i dda_dach p supply current high-speed mode tbd ?a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 ?s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 ?s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 ?s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr 100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 ?v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance load = 3 k? 250 ? sr slew rate -80h figure 18. typical inl error vs. digital code peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 53 general business information figure 19. offset at half scale vs. temperature 6.6.4 op-amp electrical specifications table 34. op-amp electrical specifications symbol description min. typ. max. unit v dd operating voltage 1.71 3.6 v i supply supply current (i out =0ma, cl=0), low-power mode tbd tbd ?a i supply supply current (i out =0ma, cl=0), high-speed mode tbd tbd ?a v os input offset voltage 3 10 mv table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. 5 preliminary freescale semiconductor, inc. general business information table 34. op-amp electrical specifications (continued) symbol description min. typ. max. unit i bias typical input bias current across the following temp range (050?c) 500 pa i bias typical input bias current across the following temp range (-40105?c) 4 na v cml input common mode voltage low 0 v v cmh input common mode voltage high vdd v r in input resistance 500 m? c in input capacitance 17 1 pf |x in | ac input impedance (f in =100khz) 50 m? cmrr input common mode rejection ratio 60 db psrr power supply rejection ratio 60 db sr slew rate ( table 36. triamp full range operating behaviors symbol description min. typ. max. unit notes i supply supply current (i out =0ma, cl=0) low-power mode 60 80 ?a i supply supply current (i out =0ma, cl=0) high-speed mode 280 450 ?a v os input offset voltage tbd tbd mv table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. 5 preliminary freescale semiconductor, inc. general business information table 37. triamp limited range operating requirements (continued) symbol description min. max. unit notes c l output load capacitance 100 pf table 38. triamp limited range operating behaviors symbol description min. typ. max. unit notes v os input offset voltage 3 5 mv table 40. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v v out voltage reference output factory trim 1.1584 1.2376 v v out voltage reference output user trim 1.193 1.197 v v step voltage reference trim step 0.5 mv v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv i bg bandgap only current 80 a 1 i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1 6.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit http://www.usb.org. 6.8.2 usb dcd electrical specifications table 43. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 ?a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 ?a i dm_sink usb_dm sink current 50 100 150 ?a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k? v dat_ref data detect voltage 0.25 0.33 0.4 v 6.8.3 usb vreg electrical specifications table 44. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 120 186 ?a i ddstby quiescent current standby mode, load current equal zero 1.1 1.54 ?a i ddoff quiescent current shutdown mode vregin = 5.0 v and temperature=25c across operating voltage and temperature 650 4 na ?a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v run mode standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 ?f table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. freescale semiconductor, inc. preliminary 5 general business information table 44. usb vreg electrical specifications (continued) symbol description min. typ. 1 max. unit notes esr external output capacitor equivalent series resistance 1 100 m? i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 ?c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 6.8.4 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 45. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 25 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspisc delay (t bs x 2) 2 ns 1 ds dspisc to dspipcs n invalid delay (t bs x 2) 2 ns 2 ds5 dspisc to dspist valid ns ds dspisc to dspist invalid 0 ns ds dspisin to dspisc input setup 1 ns ds dspisc to dspisin input hold 0 ns 1. the delay is programmable in spixctarnpssc and spixctarncssc. 2. the delay is programmable in spixctarnpasc and spixctarnasc. peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. 0 preliminary freescale semiconductor, inc. general business information ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 20. dspi classic spi timing master mode table 46. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 12.5 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 21. dspi classic spi timing slave mode peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 61 general business information 6.8.5 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 47. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 12.5 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspisc delay (t bs x 2) ns 2 ds dspisc to dspipcs n invalid delay (t bs x 2) ns ds5 dspisc to dspist valid .5 ns ds dspisc to dspist invalid -1.2 ns ds dspisin to dspisc input setup 1.1 ns ds dspisc to dspisin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum freuency of operation is reduced. 2. the delay is programmable in spixctarnpssc and spixctarncssc. . the delay is programmable in spixctarnpasc and spixctarnasc. ds ds ds1 ds2 ds ds first data last data ds5 first data data last data ds data dspipcsn dspisc (cpl0) dspisin dspist figure 22. dspi classic spi timing master mode table . slave mode dspi timing (full voltage range) num description min. max. nit perating voltage 1.1 . table continues on the next page... peripheral operating reuirements and behaviors 50 sub-family data sheet, rev. 1, /2012. 2 preliminary freescale semiconductor, inc. general business information table 48. slave mode dspi timing (full voltage range) (continued) num description min. max. unit frequency of operation 6.25 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 24 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 3.2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 19 ns ds16 dspi_ss inactive to dspi_sout not driven 19 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 23. dspi classic spi timing slave mode 6.8.6 i 2 c switching specifications see general switching specifications . 6.8.7 uart switching specifications see general switching specifications . peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 63 general business information 6.8.8 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 49. sdhc switching specifications num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed) 0 25 mhz fpp clock frequency (mmc full speed) 0 20 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 24. sdhc timing peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 64 preliminary freescale semiconductor, inc. general business information 6.8.9 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 6.8.9.1 normal run, wait and stop mode performance over a limited operating voltage range this section provides the operating performance over a limited operating voltage for the device in normal run, wait and stop modes. table 50. i2s/sai master mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 15 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 65 general business information s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 25. i2s/sai timing master modes table 51. i2s/sai slave mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 15 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 66 preliminary freescale semiconductor, inc. general business information s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 26. i2s/sai timing slave modes 6.8.9.2 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 52. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1.0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 20.5 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 67 general business information s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 27. i2s/sai timing master modes table 53. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 5.8 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 20.6 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 5.8 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 68 preliminary freescale semiconductor, inc. general business information s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 28. i2s/sai timing slave modes 6.8.9.3 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 54. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 69 general business information s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 29. i2s/sai timing master modes table 55. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 3 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 63 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k50 sub-family data sheet, rev. 1, 6/2012. 70 preliminary freescale semiconductor, inc. general business information s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 30. i2s/sai timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 56. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 8 15 mhz 2 , 3 f elemax electrode oscillator frequency 1 1.8 mhz 2 , 4 c ref internal reference capacitor 1 pf v delta oscillator delta voltage 500 mv 2 , 5 i ref reference oscillator current source base current 2 32 2 32 1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. fixed external capacitance of 20 pf. 3. refchrg = 2, extchrg=0. 4. refchrg = 0, extchrg = 10. 5. v dd = 3.0 v. 6. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 7. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current. 8. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 9. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 10. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 11. sensitivity defines the minimum capacitance change when a single count from the tsi module changes. sensitivity depends on the configuration used. the documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (c ref * i ext )/( i ref * ps * nscn) the typical value is calculated with the following configuration: i ext = 6 = 16 = 2 = 32 8.1 k50 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 1 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda rtc_clkout 2 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx sdhc0_d0 i2c1_scl spi1_sin 3 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_cts_b sdhc0_dclk 4 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts_b sdhc0_cmd spi1_sout 5 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx sdhc0_d3 6 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 7 vdd vdd vdd 8 vss vss vss 9 usb0_dp usb0_dp usb0_dp 10 usb0_dm usb0_dm usb0_dm 11 vout33 vout33 vout33 12 vregin vregin vregin 13 adc0_dp1/ op0_dp0 adc0_dp1/ op0_dp0 adc0_dp1/ op0_dp0 14 adc0_dm1/ op0_dm0 adc0_dm1/ op0_dm0 adc0_dm1/ op0_dm0 15 adc1_dp1/ op1_dp0/ op1_dm1 adc1_dp1/ op1_dp0/ op1_dm1 adc1_dp1/ op1_dp0/ op1_dm1 16 adc1_dm1/ op1_dm0 adc1_dm1/ op1_dm0 adc1_dm1/ op1_dm0 17 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 18 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 19 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 20 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 21 vdda vdda vdda 22 vrefh vrefh vrefh 23 vrefl vrefl vrefl 24 vssa vssa vssa pinout k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 73 general business information 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 25 adc1_se16/ op1_out/ cmp2_in2/ adc0_se22/ op0_dp2/ op1_dp2 adc1_se16/ op1_out/ cmp2_in2/ adc0_se22/ op0_dp2/ op1_dp2 adc1_se16/ op1_out/ cmp2_in2/ adc0_se22/ op0_dp2/ op1_dp2 26 adc0_se16/ op0_out/ cmp1_in2/ adc0_se21/ op0_dp1/ op1_dp1 adc0_se16/ op0_out/ cmp1_in2/ adc0_se21/ op0_dp1/ op1_dp1 adc0_se16/ op0_out/ cmp1_in2/ adc0_se21/ op0_dp1/ op1_dp1 27 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 28 tri0_out/ op1_dm2 tri0_out/ op1_dm2 tri0_out/ op1_dm2 29 tri0_dm tri0_dm tri0_dm 30 tri0_dp tri0_dp tri0_dp 31 tri1_dm tri1_dm tri1_dm 32 tri1_dp tri1_dp tri1_dp 33 tri1_out/ cmp2_in5/ adc1_se22 tri1_out/ cmp2_in5/ adc1_se22 tri1_out/ cmp2_in5/ adc1_se22 34 dac0_out/ cmp1_in3/ adc0_se23/ op0_dp4/ op1_dp4 dac0_out/ cmp1_in3/ adc0_se23/ op0_dp4/ op1_dp4 dac0_out/ cmp1_in3/ adc0_se23/ op0_dp4/ op1_dp4 35 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23/ op0_dp5/ op1_dp5 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23/ op0_dp5/ op1_dp5 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23/ op0_dp5/ op1_dp5 36 xtal32 xtal32 xtal32 37 extal32 extal32 extal32 38 vbat vbat vbat 39 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts_ b/ uart0_col_b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk 40 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di 41 pta2 jtag_tdo/ trace_swo/ ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do 42 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts_b ftm0_ch0 jtag_tms/ swd_dio pinout k50 sub-family data sheet, rev. 1, 6/2012. 74 preliminary freescale semiconductor, inc. general business information 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 43 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b 44 pta12 cmp2_in0 cmp2_in0 pta12 ftm1_ch0 i2s0_txd0 ftm1_qd_ pha 45 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 ftm1_ch1 i2s0_tx_fs ftm1_qd_ phb 46 pta14 disabled pta14 spi0_pcs0 uart0_tx i2s0_rx_bclk i2s0_txd1 47 pta15 disabled pta15 spi0_sck uart0_rx i2s0_rxd0 48 vdd vdd vdd 49 vss vss vss 50 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 51 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_alt1 52 reset_b reset_b reset_b 53 ptb0/ llwu_p5 adc0_se8/ adc1_se8/ tsi0_ch0 adc0_se8/ adc1_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 ftm1_qd_ pha 54 ptb1 adc0_se9/ adc1_se9/ tsi0_ch6 adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 ftm1_qd_ phb 55 ptb2 adc0_se12/ tsi0_ch7 adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts_b ftm0_flt3 56 ptb3 adc0_se13/ tsi0_ch8 adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts_ b/ uart0_col_b ftm0_flt0 57 ptb9 disabled ptb9 spi1_pcs1 uart3_cts_b fb_ad20 58 ptb10 adc1_se14 adc1_se14 ptb10 spi1_pcs0 uart3_rx fb_ad19 ftm0_flt1 59 ptb11 adc1_se15 adc1_se15 ptb11 spi1_sck uart3_tx fb_ad18 ftm0_flt2 60 vss vss vss 61 vdd vdd vdd 62 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_sout uart0_rx fb_ad17 ewm_in 63 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_sin uart0_tx fb_ad16 ewm_out_b 64 ptb18 tsi0_ch11 tsi0_ch11 ptb18 ftm2_ch0 i2s0_tx_bclk fb_ad15 ftm2_qd_ pha 65 ptb19 tsi0_ch12 tsi0_ch12 ptb19 ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_ phb 66 ptb20 disabled ptb20 spi2_pcs0 fb_ad31 cmp0_out 67 ptb21 disabled ptb21 spi2_sck fb_ad30 cmp1_out 68 ptb22 disabled ptb22 spi2_sout fb_ad29 cmp2_out 69 ptb23 disabled ptb23 spi2_sin spi0_pcs5 fb_ad28 70 ptc0 adc0_se14/ tsi0_ch13 adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extrg fb_ad14 i2s0_txd1 71 ptc1/ llwu_p6 adc0_se15/ tsi0_ch14 adc0_se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_rts_b ftm0_ch0 fb_ad13 i2s0_txd0 72 ptc2 adc0_se4b/ cmp1_in0/ tsi0_ch15 adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts_b ftm0_ch1 fb_ad12 i2s0_tx_fs pinout k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 75 general business information 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 73 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_bclk 74 vss vss vss 75 vdd vdd vdd 76 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11 cmp1_out 77 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_alt2 i2s0_rxd0 fb_ad10 cmp0_out 78 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_extrg i2s0_rx_bclk fb_ad9 i2s0_mclk 79 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb_sof_ out i2s0_rx_fs fb_ad8 80 ptc8 adc1_se4b/ cmp0_in2 adc1_se4b/ cmp0_in2 ptc8 i2s0_mclk fb_ad7 81 ptc9 adc1_se5b/ cmp0_in3 adc1_se5b/ cmp0_in3 ptc9 i2s0_rx_bclk fb_ad6 ftm2_flt0 82 ptc10 adc1_se6b adc1_se6b ptc10 i2c1_scl i2s0_rx_fs fb_ad5 83 ptc11/ llwu_p11 adc1_se7b adc1_se7b ptc11/ llwu_p11 i2c1_sda i2s0_rxd1 fb_rw_b 84 ptc12 disabled ptc12 uart4_rts_b fb_ad27 85 ptc13 disabled ptc13 uart4_cts_b fb_ad26 86 ptc14 disabled ptc14 uart4_rx fb_ad25 87 ptc15 disabled ptc15 uart4_tx fb_ad24 88 vss vss vss 89 vdd vdd vdd 90 ptc16 disabled ptc16 uart3_rx fb_cs5_b/ fb_tsiz1/ fb_be23_16_b 91 ptc17 disabled ptc17 uart3_tx fb_cs4_b/ fb_tsiz0/ fb_be31_24_b 92 ptc18 disabled ptc18 uart3_rts_b fb_tbst_b/ fb_cs2_b/ fb_be15_8_b 93 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_rts_b fb_ale/ fb_cs1_b/ fb_ts_b 94 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_cts_b fb_cs0_b 95 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx fb_ad4 96 ptd3 disabled ptd3 spi0_sin uart2_tx fb_ad3 97 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_rts_b ftm0_ch4 fb_ad2 ewm_in 98 ptd5 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_cts_ b/ uart0_col_b ftm0_ch5 fb_ad1 ewm_out_b pinout k50 sub-family data sheet, rev. 1, 6/2012. 76 preliminary freescale semiconductor, inc. general business information 100 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 99 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 100 ptd7 disabled ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 8.2 k50 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k50 sub-family data sheet, rev. 1, 6/2012. freescale semiconductor, inc. preliminary 77 general business information 60 59 58 57 56 55 54 53 52 51 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pga1_dm/adc1_dm0/adc0_dm3 pga1_dp/adc1_dp0/adc0_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga0_dp/adc0_dp0/adc1_dp3 adc1_dm1/op1_dm0 adc1_dp1/op1_dp0/op1_dm1 adc0_dm1/op0_dm0 adc0_dp1/op0_dp0 vregin vout33 usb0_dm usb0_dp vss vdd pte5 pte4/llwu_p2 pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vdd vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 ptb21 ptb20 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 25 24 23 22 21 adc1_se16/op1_out/cmp2_in2/adc0_se22/op0_dp2/op1_dp2 vssa vrefl vrefh vdda 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 ptd6/llwu_p15 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 50 49 48 47 46 45 44 43 42 41 pta18 vss vdd pta15 pta14 pta13/llwu_p4 pta12 pta4/llwu_p3 pta3 pta2 pta1 pta0 vbat extal32 xtal32 dac1_out/cmp0_in4/cmp2_in3/adc1_se23/op0_dp5/op1_dp5 dac0_out/cmp1_in3/adc0_se23/op0_dp4/op1_dp4 tri1_out/cmp2_in5/adc1_se22 tri1_dp tri1_dm tri0_dp tri0_dm tri0_out/op1_dm2 vref_out/cmp1_in5/cmp0_in5/adc1_se18 adc0_se16/op0_out/cmp1_in2/adc0_se21/op0_dp1/op1_dp1 98 ptd5 97 ptd4/llwu_p14 96 ptd3 95 ptd2/llwu_p13 94 ptd1 93 ptd0/llwu_p12 92 ptc18 91 ptc17 90 ptc16 89 vdd 88 vss 80 ptc8 ptc9 ptc10 81 82 83 ptc11/llwu_p11 84 ptc12 85 ptc13 86 ptc14 87 ptc15 100 ptd7 figure 31. k50 100 lqfp pinout diagram pinout k50 sub-family data sheet, rev. 1, 6/2012. 78 preliminary freescale semiconductor, inc. general business information how to reach us: hoe ae: wwweescaeco e ot: htt:wwweescaecosot uoe o ocatos ot ste: eescae ecocto echca oato ete ast ot roa ee oa o wwweescaecosot oe e ast a ca: eescae haete etscha h echca oato ete chatoe eche ea sh sh ea ech wwweescaecosot aa: eescae ecocto aa t heaates r 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